1. Field of the Invention
The present invention relates generally to high-speed logic circuits for use in data processing systems and in particular to CML circuit designs for implementing storage and logical registers for said data processing systems.
2. Description of the Prior Art
The evolution of electronic data processing systems has inextricably trended towards faster and more reliable systems. As part of this trend the various components used for assemblying said data processing systems have similarly evolved towards smaller, faster and denser parts. One such part affected by this evolutionary process is the working storage element or register.
The register function is notoriously old in the art: in response to control signals, the register must store a bit (or bits), of data. A register system may include means for storing a plurality of bits in parallel. Alternatively, register system may be designed serially such that it forms a shift register. If a register is built with a feedback loop such that it continues to store the data until signalled to do otherwise, the register is sometimes referred to as latch.
Current mode logic (CML) offers a relatively new circuit design technology for providing high-speed, high-density electronic parts such as registers. A prior art CML register is described in U.S. Pat. No. 3,514,640, issued Feb. 3, 1967 to D. L. Fett. However, there is a need for a CML register circuit which could be produced on a semiconductor chip of higher density. Also there is the need for a pulse generation scheme for control of input and output of data from the register system. If properly designed, a pulse generation scheme could enhance the operating characteristics of the register system as well as make it more useful as a building block within data processing systems.